This invention relates to a semiconductor device, and in particular, it relates to a structure of a metal insulator semiconductor (MIS) type field effect transistor (FET) device. This invention is most advantageously applicable to fabrication of complementary metal oxide semiconductor (CMOS) devices for improving the switching speed of the devices.
In the field of large scale integration (LSI) devices, CMOS is used widely. In order to improve the switching speed and the packing density of CMOS, reducing the channel of CMOS has been proposed.
Generally, in a conventional structure of a CMOS integrated circuit (IC), a p-type well region is formed in an n-type semiconductor substrate by introducing into a portion of the substrate a sufficient amount of a p-type impurity to compensate the substrate n-type impurity. A p-channel type MOS FET (P-MOSFET) is formed on the n-type substrate, and an n-channel type MOS FET (n-MOSFET) is formed on the p-type well region. In order to increase the switching speed and packing density of CMOS, it is advantageous to reduce the channel length. The n-MOSFET is formed on the p-type well region having an impurity of high concentration without difficulty. However, it is difficult to reduce the channel length of the p-MOSFET formed on the n-type substrate having an impurity of low concentration. One of the problems is a "punch-through effect" of the MOSFET, wherein the punch-through effect is occasionally caused on a substrate of an impurity of low concentration. When a voltage is applied across the electrode on a source region and a drain region, depletion layers from each region extend to the portion under the gate to cause a punch-through current to flow between the source region and the drain region. As a result, performance of the MOSFET is disturbed by the punch-through effect.
In a prior method for fabricating the MOSFET, a structure of a "twin-tub" has been used in order to prevent such a punch-through effect. The twin-tub has been proposed as a structure suitable for reducing channel length of MOSFETs formed on the substrate.
FIG. 1 is a schematic and partial cross-sectional view of a structure of the twin-tub of a prior art MOSFET device. A p-type well region 2 and an n-type well region 3 are formed on the surface of the semiconductor substrate 1. The well regions have the same and opposite conductivity types with high impurity concentrations compared with that of the substrate. An n-MOSFET and a p-MOSFET are formed on the well regions 2 and 3 respectively. In FIG. 1, reference numeral 1 is an n.sup.- -type silicon (Si) substrate; 2 is a p-type well region; 3 is an n-type well region; 4 is a field oxide film (isolation element); 5 is a p.sup.+ -type channel cut region; 6 is an n.sup.+ -type channel cut region; 7a and 7b are gate oxide films; 8a and 8b are gate electrodes; 9a is an n.sup.+ -type drain region; 9b is an n.sup.+ -type source region; n-MOS designates an n-channel MOSFET; and p-MOS designates a p-channel MOSFET.
In the conventional structure of the above-described "twin-tub" MOSFET device, one major drawback is that the junction capacitance between the P.sup.+ -type drain region 10a and the n-type well region 3 becomes large. The parasitic drain capacitance functions as a load in switching operations, and the switching speed of the p-channel MOSFET is decreased. When a reverse-bias voltage is applied across the source region, the switching speed of the MOSFET also is disturbed by the junction capacitance of the source region.